Technical Field
The present invention relates to a radiation detection element and a radiograph detection device. In particular, the present invention relates to a radiation detection element and a radiograph detection device in which the pixels are arranged in the form of a honeycomb.
Related Art
FPDs (Flat Panel Detectors), in which an X-ray sensitive layer is disposed on a TFT (Thin Film Transistor) active matrix substrate and that can convert X-ray information directly into digital data, have been used as radiation detection elements in most radiograph detection devices in recent years. Decreasing the pixel size is effective in improving the resolution of the FPD. Pixel size contributes to an improvement in resolution particularly in direct-conversion-type radiation detection elements that use selenium (Se) in the photoelectric conversion layer that absorbs radiation and converts the radiation into charges. Therefore, in recent years, attempts have been made to improve image quality by making the pixel size more fine.
On the other hand, in an FPD, the amount of charge that can be collected decreases in proportion to the reduction in pixel size, and the S/N decreases. Therefore, even if the resolution improves, the comprehensive image quality DQE deteriorates. Thus, improving the resolution, maintaining the S/N, and aiming for an improvement in the utilization efficiency of light by making the shape of the pixels into a hexagonal shape or the like and arraying the pixels in the form of a honeycomb has been proposed (see, for example, Patent Documents 1 through 4).
For example, Patent Document 1 describes a radiation detection element 200 of a structure in which, as shown in FIG. 14, numerous, plural, hexagonal pixels 20 are arrayed in a two-dimensional form while adjacent to one another, and are arrayed in the form of a honeycomb. Each of the pixels 20 has a thin-film transistor 4 (hereinafter called TFT switch 4).
Further, plural scan lines 101, that extend in the X direction (row direction) that is the lateral direction in FIG. 14 and that are disposed so as to be lined-up in the Y direction (column direction) that is orthogonal to the X direction, and plural data lines 3, that intersect these scan lines 101 and extend in the Y direction while bending along peripheral edges of the pixels 20, are disposed at the radiation detection element 200. Further, at the radiation detection element 200, plural common ground lines 30 are disposed between the plural data lines 3 without intersecting these plural data lines 3 and while intersecting the plural scan lines 101.
As shown in FIG. 14, the scan lines 101 are disposed one-by-one with respect to pixel rows 20a˜20d that are each formed from plural pixels, and are connected to gate electrodes 2 that structure the TFT switches 4 that are formed at the respective pixels 20. A source electrode 9 and a drain electrode 13 that structure the TFT switch 4 are formed at the upper layer of the gate electrode 2 and the like. The data lines 3 are formed, together with the source electrodes 9 and the drain electrodes 13, in the wiring layer in which the source electrode 9 and the drain electrode 13 are formed. The data lines 3 are disposed so as to be bent along peripheral edges of the pixels 20 so as to detour between adjacent pixels and pixels, and are connected to the source electrodes 9 that are formed at the pixels 20 of the respective pixel rows. Namely, the data line 3 extends in the column direction while running along three sides that are continuous among the peripheral edges (the six sides) of each pixel 20.
Further, the radiation detection element 200 is a structure in which the arrangement of the TFT switches 4 at the respective pixels 20 differs per pixel row 20a˜20d. More concretely, at each pixel of the pixel rows 20a-20d, the TFT switch 4 is disposed at a region that is surrounded by a line segment, that divides the pixel in two in the lengthwise direction, and the three sides at which the data line 3 is continuously provided among the peripheral edges of the pixel.
Further, at the pixels of the pixel row 20a, the TFT switches 4 are disposed in the regions at the right side halves of the pixels 20, and, at the pixels of the pixel row 20b that is positioned at the tier beneath the pixel row 20a, the TFT switches 4 are disposed in the regions at the left side halves of the pixels 20. Thereafter, similarly, the TFT switches 4 are disposed in the regions at the right side halves of the pixels 20 at the pixel row 20c, and are disposed in the regions at the left side halves of the pixels 20 at the pixel row 20d, respectively.
By arranging the TFT switches 4 in this way, at the pixels 20 that are positioned in the pixel row 20a, the source electrodes 9 of the TFT switches 4, that are disposed in the regions at the right side halves of the pixels, are connected to the data line 3 that is provided continuously at the three sides of the regions at the right side halves of the pixels. Further, at the pixels 20 of the pixel row 20b, the source electrodes 9 of the TFT switches 4, that are disposed in the regions at the left side halves of the pixels, are connected to the data line 3 that is provided continuously at the three sides of the regions at the left side halves of the pixels. The same holds for the pixel row 20c and the pixel row 20d. The source electrodes 9 of the TFT switches 4 are connected to the data line 3 that is provided continuously at the three sides of the regions at the right side halves of the pixels at the pixel row 20c and at the three sides of the regions at the left side halves of the pixels at the pixel row 20d. 
Namely, in the radiation detection element 200 shown in FIG. 14, the orientation of the TFT switches 4 is different at the pixel rows of the 2N+1st tiers (N is an integer) in the Y direction (the odd-numbered pixel rows), and at the pixels rows of the 2N+2nd tiers (the even-numbered pixel rows). Namely, the positional relationship of the source electrode 9 and the drain electrode 13 in the X direction is inverted.
Patent Document 1: PCT/JP2012/068722
Patent Document 2: Japanese Patent Application Laid-Open (JP-A) No. 2003-255049
Patent Document 3: Japanese Patent Application Laid-Open (JP-A) No. 2011-109012
Patent Document 4: Japanese Patent Application Laid-Open (JP-A) No. 2011-146587
However, in a structure in which the orientation of the TFT switches 4 changes per tier as described above, if the position of the photomask is offset at the time of fabricating the TFT switches 4, there is the problem that the parasitic capacitance of the TFT switches 4, and concretely, parasitic capacitance Cgdt between the gate and the drain and parasitic capacitance Cgst between the gate and the source vary cyclically per tier.
For example, at the time of forming the data layer, in which the source electrodes 9 and the drain electrodes 13 are disposed, on the gate layer in which the gate electrodes 2 are disposed, even in a case in which the position of the photomask is offset in the Y direction, the directions of the positional offset between the gate and the drain and the positional offset between the gate and the source are the same direction at the pixel rows of the 2N+1st tiers and the pixel rows of the 2N+2nd tiers, and therefore, the parasitic capacitances Cgdt, Cgst do not vary cyclically per tier.
On the other hand, if the position of the photomask is offset in the X direction, the positional offset between the gate and the drain and the positional offset between the gate and the source vary in different directions at the pixel rows of the 2N+1st tiers and the pixel rows of the 2N+2nd tiers. Therefore, the changes in the parasitic capacitances Cgdt, Cgst per tier vary cyclically per tier such as, for example, the parasitic capacitances Cgdt, Cgst both increase at the pixels of the 2N+1st tiers and the parasitic capacitances Cgdt, Cgst both decrease at the pixels of the 2N+2nd tiers, and image artifacts arise.
This problem is described more concretely.
In the radiation detection element 200 such as described above, even in cases in which radiation is not being irradiated, uniform offset charges are accumulated due to various factors. The accumulated offset charges contain charges that have leaked from the radiation detection element and feed-through charges of the TFT switches 4. Among these, it is the feed-through charges that are problematic.
Here, given that the feed-through charge due turning on/off the gate of the TFT switch 4 of the pixel electrode is Qft1, Qft1 is expressed by the following formula.
                                                                        Qft                ⁢                                                                  ⁢                1                            =                            ⁢                              Qft_on                +                Qft_off                                                                                        =                            ⁢                                                [                                                            Cgst                      ⁡                                              (                        on                        )                                                              -                                          Cgst                      ⁡                                              (                        off                        )                                                                              ]                                ×                Vpp                                                                                        =                            ⁢                              Δ                ⁢                                                                  ⁢                Cgst                ×                Vpp                                                                        (        1        )            
Here, Qft_on is the charge at the time when the gate changes from off to on, Qft_off is the charge at the time when the gate changes from on to off, Cgst(on) is the parasitic capacitance between the gate and the source at the time when the gate changes from off to on, Cgst(off) is the parasitic capacitance between the gate and the source at the time when the gate changes from on to off, ΔCgst is the difference between Cgst(on) and Cgst(off), and Vpp is the power source voltage.
On the other hand, in actuality, charges that are generated at the drain electrode side also are transmitted through the signal lines and are directly read-out by the amp circuits, and, given that this component is Qft2, Qft2 is expressed by the following formula.
                                                                        Qft                ⁢                                                                  ⁢                2                            =                            ⁢                                                Qft                  ⁢                                                                          ⁢                  2                  ⁢                  _on                                +                                  Qft                  ⁢                                                                          ⁢                  2                  ⁢                  _off                                                                                                        =                            ⁢                                                [                                                            Cgdt                      ⁡                                              (                        on                        )                                                              -                                          Cgdt                      ⁡                                              (                        off                        )                                                                              ]                                ×                Vpp                                                                                        =                            ⁢                              Δ                ⁢                                                                  ⁢                Cgdt                ×                Vpp                                                                        (        2        )            
Here, Qft2_on is the charge at the time when the gate changes from off to on, Qft2_off is the charge at the time when the gate changes from on to off, Cgdt(on) is the parasitic capacitance between the gate and the drain at the time when the gate changes from off to on, Cgdt(off) is the parasitic capacitance between the gate and the drain at the time when the gate changes from on to off, and ΔCgdt is the difference between Cgdt(on) and Cgdt(off).
From above formulas (1) and (2), the entire feed-through charge Qft is expressed by the following formula.Qft=Qft1+Qft2=[ΔCgdt+ΔCgst]*Vpp  (3)
Further, in a case in which the position of the photomask is offset in the X direction at the time of fabricating the TFT switches 4 as described above, the values of ΔCgdt and ΔCgst fluctuate in the increasing direction at ones of the pixels of the 2N+1st tiers and the pixels of the 2N+2nd tiers, and in the decreasing direction at the others. Due thereto, the feed-through charges vary regularly per tier of pixel row. Therefore, for example, at the pixel rows of the 2N+2nd tiers, the offset values become high as compared with the pixel rows of the 2N+1st tiers, and image artifacts arise.